1. Field of the Invention
The invention relates to a high voltage semiconductor device, and more particularly, to a lateral-diffusion metal-oxide semiconductor (LDMOS) device with high breakdown voltage and low on-state resistance (Ron).
2. Description of the Prior Art
Controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation have been largely integrated together to achieve a single-chip system. The power device, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) or lateral diffusion MOS (LDMOS), has been employed to increase power switching efficiency and decrease the loss of energy resources. It is often required that the switching transistors withstand high breakdown voltages and operate at a low on-resistance.
Double diffuse drain (DDD) technology has been extensively applied to the source/drain (S/D) in order to provide a higher breakdown voltage. The DDD structure suppresses the hot electron effect caused by the short channel of the MOS transistor to further avoid electrical breakdown of the source/drain under high operational voltages. The LDMOS transistors are particularly prevalent because they can operate with a high efficiency and their planar structure allows for easy integration on a semiconductor die with other circuitry.
A conventional LDMOS is typically formed in a substrate having a first conductive type, such as a p-type semiconductor substrate for a LDNMOS, in which the p-type substrate also includes a deep n-well and a p-well and a n-well disposed in the deep n-well. A drain region of the LDNMOS is disposed in the n-well, a source region is disposed in the p-well, and the drain region and the source region are laterally connected to a gate structure of the LDMOS.
However, the doping concentration of the deep n-well fabricated by conventional method is typically uniform, hence the concentration difference at the PN junction between the deep n-well and the p-well is substantially high, which limits the LDMOS device to obtain a satisfactory breakdown voltage. If the concentration of the deep n-well were to be lowered to achieve a higher breakdown voltage, the concentration of the surrounding device would be affected immediately. Hence, how to improve the current process for fabricating a LDMOS device with higher breakdown voltage has become an important task in this field.